1. Field of the Invention
The present invention relates to a pattern correction method, which corrects layout data for a circuit pattern of a semiconductor integrated circuit, and a pattern correction apparatus. In particular it relates to an optical proximity correction (OPC) pattern correction method, which corrects for the optical proximate effect, and a pattern correction apparatus.
2. Description of the Related Art
Accompanying the miniaturization and increased integration of semiconductor integrated circuits, prevention of decreases in yield due to the optical proximate effect during the photolithography process has become an important issue. More specifically, in the case of forming a circuit pattern using the photolithography process, due to the optical proximate effect, the edge of the actually exposed and finished interconnect pattern is shortened in comparison with layout patterns such as those designed using computer-aided design (CAD) system. This phenomenon is called xe2x80x9cshorteningxe2x80x9d. As the circuit is further miniaturized and line width becomes narrow, the shortening of the exposed pattern becomes remarkable. When shortening occurs, the VIA contact hole connecting interconnects of different levels may be incompletely covered by the metal interconnect of the upper level or lower level. In addition, the shortening due to the optical proximate effect occurs not only in the metal interconnect pattern, but also in the VIA pattern connecting the interconnect pattern between the different levels. In the case where shortening occurs in the VIA pattern, VIA resistance rises remarkably, and in the worst case, disconnection may occur.
Therefore, in order to compensate for post-exposure shortening before it occurs, optical corrective processing called optical proximity correction (OPC) is applied to the metal interconnect pattern and layout data of VIA pattern in the design phase.
In a generally used OPC processing method, a correction target edge of the metal interconnect to be connected through a VIA is first extracted based on the designed layout data. The distance between the extracted correction target edge and a proximal graphics pattern is calculated. Then, referencing a rule table, correction is applied in only the amount of correction corresponding to the calculated distance. Such OPC processing is achieved through a graphics processing function provided in the general design rule checker (DRC) tool or in combination with the DRC function. In addition, there are also cases where a specific function is developed and used.
In OPC processing, as the targets for correction are extracted one by one, the proximal graphics pattern must be searched and the distance to the graphics pattern must be calculated. In the case of a large-scale integrated circuit, since the number of metal interconnects and VIA graphics is huge, a great deal of time is required to perform graphics processing and distance calculation for the OPC processing.
Moreover, since the optical proximate effect at the end of the interconnect feels real influence from the surrounding two-dimensional environment, it is necessary to judge the proximal status of the surrounding graphics. In the OPC processing method, the surrounding environment is judged in relation to only one direction, for example, in relation to only the X direction or Y direction of an XY plane. As a result, correction accuracy is poor, and ultimately satisfactory accuracy cannot be achieved in the post-exposure pattern created.
In a first aspect of the present invention, a pattern correction method includes a) receiving design layout data of a pattern designed by an automated design unit; b) determining an environmental profile based on whether or not another graphics pattern exists in the surroundings of a cell for each correction target cell included in the design layout data; c) replacing with a prescribed cell name of a correction pattern corresponding to the determined environmental profile by referencing the cell replacement table; and d) creating the OPC correction layout data by importing an OPC correction pattern corresponding to the cell name from a cell library.
In a second aspect of the present invention, a pattern correction program causes an OPC processing unit in a pattern correction apparatus to: a) determine the environmental profiles in relation to each correction target cell included in design layout data entered in the pattern correction apparatus; b) replace with a prescribed cell name of a correction pattern corresponding to the determined environmental profile by referencing a cell replacement table stored in a memory area of the pattern correction apparatus in advance; and c) search the cell library stored in the memory area of the pattern correction apparatus in advance, and import an OPC correction pattern corresponding to the replaced cell name.
In a third aspect of the present invention, a pattern correction apparatus includes: a) an input/output unit; b) an environmental profile determination unit, which determines the environment of the surrounding pattern for each correction target cell included in the design layout data entered from the input/output unit; c) a cell replacement table, which stores all assumable environmental profiles by associating with the cell names that are coordinated in one-by-one correspondence with each; d) a cell library, which indexes and stores the cell names with the OPC correction patterns for the environmental profile associated with the respective cell names; e) a replacement layout data creation unit, which reads in the replacement cell name corresponding to the environmental profile and creates the replacement layout data by referencing the cell replacement table; and f) an OPC correction pattern creation unit, which imports the OPC correction pattern corresponding to the cell name from the cell library based on the replacement layout data.